1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly, to a test circuit that shortens the time required to test semiconductor memory devices and a semiconductor memory device having the same.
2. Description of the Related Art
Since the beginning of their development, semiconductor memory devices have progressed significantly, with continual increases in performance and integration. As memory sizes increases, the time required to test the memories also increases. The increased test time delays the production cycle. Thus, efforts to shorten test times are ever on-going. Circuits have been designed and added to semiconductor devices to reduce test time. Meanwhile, in order to improve the input and output speed of semiconductor memory devices, semiconductor memory devices include a plurality of banks. A plurality of bits can be simultaneously inputted to/outputted from semiconductor memory devices including a plurality of banks.
Generally, when one-time row active and data input and output commands are applied in a normal operation mode of semiconductor memory devices, only one word line is selected in one bank corresponding to an address input from the outside. Information stored in a memory cell outputted onto a selected word line is amplified by a bit line sense amplifier and then outputted to the outside. For all word lines to be selected by a row active command, a one-time row active command must be applied at times which are equivalent to the number of banks multiplied by the number of word lines within a bank. All of the components involved in inputting/outputting data to/from a semiconductor memory device must be tested in order to ensure that the device functions properly. One can readily appreciates that as memory size becomes more dense, the time required for testing the increased memory locations and support circuits must also increase.
One way to shorten test time in a semiconductor memory device is the use of a refresh cycle reduction (RCR) mode. In the RCR mode, a plurality of banks are selected by a row active command. Therefore, a plurality of word lines are simultaneously activated by a one-time row active command, which allows a reduction in the test time. However, in this mode, since word lines within a plurality of banks are selected at the same time, more bit line sense amplifiers are operated at the same time, and more current is consumed accordingly. Since there is a limit to the amount of consumable current in a semiconductor memory device, the number of word lines which can be activated at the same time in a RCR mode is limited. Accordingly, a need exists for a device and method for conducting tests of a semiconductor memory device in a speeding fashion while minimizing current consumption.